PSEUDEC: implementation of the computation-intensive PARTRAN functionality using a dedicated on-line CORDIC co-processor

This paper describes PSEUDEC, a dedicated co-processor and the rationale behind it's design. The nal goal of our work is to present a single chip solution with low power consumption for an advanced digital hearing aid based on a parameterized transformation of speech (PARTRAN). Characterization of the constituent parts of the PAR-TRAN algorithm shows, that it is well suited for implementation on a heterogeneous architecture. The design strategy used identiies a subset suited for implementation on dedicated hardware, with computational complexity roughly equivalent to the performance of a standard 10 MIPS DSP. The subset of PARTRAN implemented by PSEUDEC performs PSEUdo DEComposition of a 12th order LPC polynomial. An adapted algorithm displays improved dynamic range compared to a conventional solution suited for DSP's, calculating the amplitude spectrum rather than the power spectrum. Highly pipelined CORDIC-units optimized for the application replaces complex multiplication, trigonometric operations (for e jw) and square root (for jaj = p a 2 r + a 2 i), exploiting the power of CORDIC operations in advanced DSP algorithms. PSEUDEC uses redundant data representation and bit-serial arithmetic, most signiicant digit rst (ON-LINE arithmetic) for eecient implementation of operators and for ee-cient (inter-operator) communication. The inherent nature of ON-LINE arithmetic and the operators used allows for fast and eecient implementation even when using ordinary standard cells.